Field of the Invention
The invention relates in general to a phase detector, and more particularly to a phase detector capable of processing data signals having multiple transmission rates.
Description of the Related Art
A clock data recovery apparatus is a circuit extensively applied in an electronic signal receiving system. FIG. 1(A) shows a functional block diagram of a typical clock data recovery apparatus. A phase detector 11 samples an input data signal DIN using a clock signal CLK, and generates a control signal according to the sample result to indicate whether the frequency of the clock signal CLK should be increased or reduced. The control signal adjusts a control voltage that a charge pump 12 and the a low-pass filter (LPF) 13 output. The control voltage is provided to a voltage-controlled oscillator (VCO) 14 to change the frequency of the clock signal CLK. In certain data recovery apparatuses, as shown in FIG. 1(A), a part of the sample result generated from the input signal DIN by the phase detector 11 can directly become a recovered signal DOUT.
FIG. 1(B) shows a partial functional block diagram of the phase detector by taking an Alexander phase detector as an example. To adapt to such phase detector architecture, the clock signal CLK outputted by the VCO 14 includes four clock signals having the same frequency but different phases. As the frequency of the clock signal CLK is about a half of the transmission rate of the input data signal DIN, this phase detector is referred to as half-rate architecture. As shown in FIG. 1(B), flip-flops 111A to 111D in the phase detector 11 sample the data signal DIN using rising edges of clock signals CLK0, CLK180, CLK90 and CLK270 respectively having phases of 0°, 90°, 180° and 270° to generate four sample results D0, D1, Q0 and Q4. The sample results D0 and D1 correspond to two adjacent sets of data, and the sample results Q0 and Q1 correspond to an intersection of the two adjacent sets of data. Generally known to one person having ordinary skill in the art, performing an appropriate exclusive-OR (XOR) logic operation on the sample results D0, D1, Q0 and Q1 may generate a control signal that causes charging or discharging the charge pump 12 to further selectively adjust the frequency of the clock signal CLK.
In many communication standards, the input data signal DIN is designed to have different transmission rates under different communication modes. For example, in High Definition Multimedia Interface (HDMI), the transmission rate of data signals is between 250 Hz and 3.4 KHz. In practice, rendering the frequency range of clock signals generated by the VCO to be as wide as the range of the transmission rate of data signals is extremely challenging. Thus, as shown in FIG. 1(C), for a communication standard having multiple transmission rates, a frequency divider 16 and a multiplexer 17 may be additionally provided between the VCO 14 and the phase detector 11 of the clock data recovery apparatus. By dividing the frequency of an original clock signal CLKORG outputted from the VCO 14 using the frequency divider 16, clock signals having different frequencies can be obtained. In this example, the frequency divider 16 provides the clock signal CLK0 having the same frequency as the original clock signal CLKORG, a clock signal CLK_DIV2 having a frequency divided to one-half, and a clock signal CLK_DIV4 having a frequency divided to one-fourth. If the original clock signal CLKORG outputted from VCO 14 includes clock signals having the same frequency but different phases, the frequency divider 16 may divide these four clock signals to provide the phase detector 11 with frequency divided clock signals having four different phases.
The phase detector 11 is usually designed to adopt one single type of circuit architecture, e.g., full-rate architecture, or half-rate architecture shown in FIG. 1(B). When the transmission rate of the input data signal DIN is changed, the multiplexer 17 is required to switch to a set of clock signals having a more appropriate frequency for the phase detector 11. For example, when the transmission rate of the input data signal DIN is reduced to one-half, the multiplexer 17 may switch from outputting the clock signals of the clock signal CLK0 having four phase to outputting the clock signals of the clock signal CLK_DIV2 having four phases, so as to keep the relationship between the transmission rate of the data signals and the frequency of the clock signals unchanged. Compared to the method rendering the clock frequency generated by the VCO 14 to cover the range of the transmission rate of data signals, the specification requirements of the clock data recovery apparatus associated with the VCO 14 in FIG. 1(C) can be less demanding and hardware costs can thus be reduced.
The amount of jittering is an important index when the performance of a clock data recovery apparatus is evaluated, and is closely correlated with the quality of signals received. In general, as the path passed gets longer and the number of circuit elements contributing the jittering gets larger, the amount of jittering in the signals becomes larger. Thus, the frequency divider 16 and the multiplexer 17 additionally provided in FIG. 1(C) cause an increase in the amount of jittering in the clock signal CLK. Even the amount of jittering of the clock signal CLK0, which has the same frequency as the original clock signal CLKORG and need not be processed by the frequency divider 16, is inevitably affected by negative influences of the multiplexer 17. To counteract the increased amount of jittering caused by the frequency divider 16 and the multiplexer 17, the VCO 14 is usually required to generate original clock signals CLKORG having a better quality, meaning that hardware costs of the VCO 14 are again increased. In contrast, if the VCO 14 having a better signal quality but higher costs is not adopted in FIG. 1(A), the frequency divider 16 and the multiplexer 17 may cause degraded performance of the clock data recovery apparatus.